entity test is    port(qout:out std_logic;  clkin,clrin:in std_logic);

end test;

architecture structual of test is component dfcib    port(d:in std_logic; clk:in std_logic;  clr:in std_logic;  q:out std_logic);

end component;

entity bingruchuanchu is port(clk,input1,input2,input3,input4,input5,input6,input7:in std_logic;

                                                             output:out std_logic);

end entity;

architecture guocheng of bingruchuanchu is    signal   chucun:std_logic_vector(6 downto 0);    

entity clk_div is    

port(clk:in std_logic;          clk_div4,clk_div2:out std_logic);

end clk_div;

architecture rtl of clk_div is signal count:std_logic_vector(1 downto 0 );

entity clk_div7 is port(clk:in std_logic;          

                                      clk_div_7:out std_logic);

end clk_div7;

architecture rtl of clk_div7 is signal count :std_logic_vector(2 downto 0);

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;