library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity bingchuan is port(clk,input:in std_logic;        

                                          output1,output2,output3:out std_logic);

end entity;

architecture guocheng of bingchuan is  signal chucun:std_logic_vector(2 downto 0);      

begin      

process(clk)      

variable i:integer:=0;    

begin        

if rising_edge(clk)then            

if(i = 2)then                              

output1<=chucun(0);                

output2<=chucun(1);                

output3<=input;                

i:=0;              

else                      

chucun(i)<=input;                

i:=i+1;                            

end if;        

end if;

end process;

end guocheng;

作者：菜鸟学编程@Bo-Blog
地址：http://www.node-net.org/read.php?10
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