library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity clk_div7 is port(clk:in std_logic;          

                                      clk_div_7:out std_logic);

end clk_div7;

architecture rtl of clk_div7 is signal count :std_logic_vector(2 downto 0);

begin        

process(clk)        

constant md :std_logic_vector(2 downto 0):="110";    

begin            

if rising_edge(clk)then          

if(count = md)then              

count<=(others =>'0');              

clk_div_7 <='1';            

else              

count <= count+1;              

clk_div_7 <= '0';            

end if;        

end if;    

end process;

end rtl;

作者：菜鸟学编程@Bo-Blog
地址：http://www.node-net.org/read.php?11
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